Here is the simulation testbed HDL I used. The suffixes are just my own preference and how I keep track of what the signals are. Please answer me asap, in case it would be defective, i need to return it. Is this going to be remedied anytime soon? Windows XP Service Pack 2.

Uploader: Braktilar
Date Added: 11 August 2010
File Size: 66.71 Mb
Operating Systems: Windows NT/2000/XP/2003/2003/7/8/10 MacOS 10/X
Downloads: 28920
Price: Free* [*Free Regsitration Required]

Technical Support Need Help? Is this going to be remedied anytime soon? This is just speculation on my part though. You are commenting using your Twitter account. Thank you for reply. There is a minimum amount of time from the activate command to when the data is ready to be read or written. Datasheets are always written with the assumption that you know what they are talking about, and just about all the information I could find on SDRAM operation also assumed some previous knowledge about how SDRAM works.

A refresh cycle needs to be issued at least once every 7. SDRAM does work better with an intelligent controller that keeps track of reads and writes, can open multiple banks at once, and pull data back in busts. I even contacted them through the XPS and got the run around. I currently have it set to x so I can read it, but it drops it down and I lose inches on 82830mo side.


Hey all, I much preferred Win 10 while it was in development so grabbed it as soon as it was released. You can use these HTML tags. You are commenting using your WordPress. The program throws an error code.

SDRAM controller for low-end FPGAs

And the only product in Dell’s system is an old XPS. If you introduce a row address then you are only looking at a single bit location, surely?

There were some later issues with using the falling edge, and all the strange issues were resolved by using the rising edge and buffering the output data. To really display anything useful though I need to have a large enough display buffer and my next step was to take on the xdram task of creating an SDRAM controller.

Each bank is configured as x-rows of y-bits columns.

I have written some verilog programs. I didn’t find anything on the DELL.

August 20, at 6: I’ve just bought a PD, my screen goes black sometimes randomly, like a mac sdam has pointed out somewhere in the forum.

By using our website and services, you expressly agree to the placement of our performance, functionality and advertising cookies.


January 28, at 5: Are you the publisher? The clock input must be MHz.

DELL-Chris M’s Activities

November 29, at 4: March 31, at 7: I can make video interfaces from 74xx logic and I can work with logic expressions. Using my existing Dell ST monitor. The cumulative time for the SDRAM I am using is 70ns from activate to activate, which becomes the minimum and fixed access time for my controller. Controler is that in display properties, it keep showing 59hz, instead of It is bad enough I have to grab the drivers from a different computer, but finding out that even that will not allow the laptop to hook up to the internet in order to get the rest of the drivers is just frustrating.

The SDRAM takes care of determining what row to refresh during a refresh cycles, so all you have to worry about is issuing a refresh command at least once every 7.

Start the discussion

Leave a Reply

Your email address will not be published. Required fields are marked *